| Document Date: 2012-01-18 11:44:30
Open Document File Size: 354,66 KBShare Result on Facebook
Company Intel / Consolider CSD2007 / / Currency pence / / / Event FDA Phase / / Facility Advanced Conflict Recording In STALL / The BK bar / Josep Torrellas University of Illinois / In STALL / STALL T1 / STALL Design When / SQ-EE bar / / IndustryTerm software productivity / singlecore processor / energy consumption / chunk-based protocols / parallel software productivity / multicore chip / database systems / complicated cache coherence protocol / times more hardware / research / multiprocessor hardware / software places chunk termination commands / much less hardware / cache replacement algorithms / local and global chunk-based protocols / multi-socket systems / simpler hardware / cores/chip / version management / cycle detection algorithm / processor hardware / / NaturalFeature AritMean_OR AritMean_ST Streamcluster_OR Streamcluster_ST Raytrace_OR Raytrace_ST Radix_OR Radix_ST Radiosity_OR Radiosity_ST Ocean_OR Ocean / / Organization University of Illinois / National Science Foundation / Universidad de Valladolid / SESC / Illinois-Intel Parallelism Center / / Person Ti / Benjamin Sahelices / / Position same producer / Governor / Last Writer / writer / producer / / Product BulkSMT / Advanced SSG / L2 / BulkSMT Processor / / ProgrammingLanguage FP / / ProvinceOrState Illinois / Connecticut / / RadioStation 1.0 RAW 0.75 / / Technology cycle detection algorithm / local protocol / SSG algorithm / cache replacement algorithms / SMT processor / chunk-based protocols / 4 cores/chip / Squash Set Generation algorithm / multicore chip / SRAM / SMT processors / complicated cache coherence protocol / BulkSMT processor / shared memory / flash / singlecore processor / / URL http /
SocialTag |
BulkSMT: Designing SMT Processors for Atomic-Block Execution∗ Xuehai Qian, Benjamin Sahelices and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract