Configurable M -factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design Gabriel Falcao∗1,2 , Marco Gomes1,2 , Vitor Silva1,2 , Leonel Sousa3,4 and Joao Cacheira2 1 Instituto

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Date: 2012-03-09 10:48:10 Error detection and correction Coding theory Low-density parity-check code Digital Video Broadcasting DVB-S2 Forward error correction Turbo code Tanner graph Noisy-channel coding theorem		Configurable M -factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design Gabriel Falcao∗1,2 , Marco Gomes1,2 , Vitor Silva1,2 , Leonel Sousa3,4 and Joao Cacheira2 1 Instituto Add to Reading List Source URL: www.inesc-id.pt Download Document from Source Website File Size: 813,43 KB Share Document on Facebook

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