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Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs  Israel Koren and Zahava Koren
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Document Date: 2011-01-27 16:46:18

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File Size: 319,51 KB

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City

Austin / /

Company

VLSI Systems / /

Currency

USD / /

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Event

Product Issues / /

Facility

Computer Engineering University / /

IndustryTerm

ultiprocessor systems / ulti-bank memory whic / half-chip / sub-micron process technologies / /

Organization

National Science Foundation / Electrical and Computer Engineering University of Massac / /

Person

Koren Departmen / /

Position

negative binomial model for the defect distribution / designer / /

Product

rows / arrays / row / /

ProvinceOrState

Texas / /

Technology

sub-micron process technologies / SRAM / same chip / operational half chip / /

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