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Computing / Graphics hardware / Image processing / Shading / Rasterisation / Deferred shading / Graphics pipeline / Spatial anti-aliasing / Rendering / Computer graphics / 3D computer graphics / Imaging


BREAKING THE FRAME-BUFFER BOTTLENECK: THE CASE FOR LOGIC-ENHANCED MEMORIES John Poulton, John Eyles, Steven Molnar, Henry Fuchs University of North Carolina at Chapel Hill A central problem in designing interactive grap
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Document Date: 1998-05-07 14:40:06


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File Size: 86,08 KB

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Company

Rambus / Silicon Graphics / Cached DRAMs / /

Event

Man-Made Disaster / /

Facility

Chapel Hill A / Henry Fuchs University of North Carolina / /

IndustryTerm

wide-word processor / few dozen chips / few processors / interactive graphics systems / commodity product / graphics hardware systems / experimental graphics systems / memory device / announced memory devices / memory devices / energy / pixel processor / graphics applications / extreme solution / A-buffer algorithms / rasterization algorithm / logic-enhanced memory chip / region processors / tiny processors / geometry processing speeds / parallel solutions / rasterizer/frame buffer systems / Geometry processing / large custom memory-intensive chip / tiny pixel-local processors / 3D systems / geometry processor / geometry-processing stage / z-buffer algorithm / memory chips / graphics systems / vector dot products / speed graphics systems / highend graphics systems / /

Organization

University of North Carolina / Multiple / ASIC / MIMD / Single / /

Person

John Eyles / Phong Shading / Steven Molnar / /

Position

single wide-word processor / author / Screen-space primitive data Screen-space primitive data Wide-word Processor / /

ProvinceOrState

North Carolina / /

Technology

semiconductor / same chips / RAM / rasterizing processors / z-buffer algorithm / A-buffer algorithms / geometry processor / 10 Screen-space primitive data Screen-space primitive data Wide-word Processor Pixel-parallel Processors / rasterization algorithm / pixel processor / memory-intensive chip / random access / SRAM / few dozen chips / memory chips / integrated circuits / A-buffer algorithm / video RAM / ASIC / wide-word processor / relatively few processors / memory chip / Processor Organization The processors / tiny pixel-local processors / rasterizing processor / VRAM memory chips / Caching / region processors / generally determined using the z-buffer algorithm / /

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