A Loop Acceleration Technique to Speed Up Verification of Automatically-Generated Plans Robert P. Goldman and Michael J.S. Pelican and David J. Musliner SIFT, LLC 211 N. First St. Minneapolis, MN 55401

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Date: 2013-04-15 04:52:48 Applied mathematics Computer science Model checkers Formal methods Logic in computer science Formal verification Model checking State transition system Uppaal Model Checker Models of computation Theoretical computer science Automata theory		A Loop Acceleration Technique to Speed Up Verification of Automatically-Generated Plans Robert P. Goldman and Michael J.S. Pelican and David J. Musliner SIFT, LLC 211 N. First St. Minneapolis, MN 55401 Add to Reading List Source URL: icaps11.icaps-conference.org Download Document from Source Website File Size: 383,04 KB Share Document on Facebook

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