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IEEE standards / Cybernetics / FIFO / Inter-process communication / Embedded systems / Joint Test Action Group / Vvvv / Processor register / Computing / Electronics / Concurrent computing


SP04/SP05 Backplane Interfaces
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Document Date: 2007-08-20 10:25:03


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File Size: 402,94 KB

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Company

Data Register Group / A15 A14 A13 A12 A11 A10 A9 SA / Fast Control Group / Status Register Group / Action Register Group / Reserved Group / Used Subtotal Total 8 34 The Clock Group / Address Register Group / Reload Group / Control/Status Register Group / MA DD Fx VM Page Action Register Group / /

Facility

University of Florida July / Lev Uvarov SP Backplane Interfaces Petersburg Nuclear Physics Institute / /

Organization

Federal Communications Commission / Eta / Lev Uvarov SP Backplane Interfaces Petersburg Nuclear Physics Institute / European monetary union / Clock and Control Board / University of Florida / /

Person

Lev Uvarov Alex / Reset Link Counter Reset / Lev Uvarov / /

Position

Alignment FIFO Status Test FIFO Status Spy / FIFO Status F3 Spy FIFO Status F4 Spy / Spy / Control/Status Alignment FIFO Delay Test FIFO Configuration Spy / Barrel Test FIFO Status Barrel Spy / Manager / Clock Manager / Pointer F1 Spy FIFO Status F2 Spy / Status Barrel Spy FIFO Status Muon Sorter Spy / Bus Scan Controller / FIFO Status F4 Spy FIFO Status F5 Spy / FIFO Status F2 Spy FIFO Status F3 Spy / /

ProgrammingLanguage

FP / /

ProvinceOrState

Massachusetts / /

RadioStation

AM AM / /

Technology

FPGA / 20 68 70 STS_CD STS_CA STS_CCB STS_ANA STS_MWA STS_BC0 STS_AF Chip Data Status Chip / Finite State Machine / Identifier Chip / SRAM / /

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