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Computer architecture / Computing / Computer engineering / Concurrent computing / Central processing unit / Thread / Scheduling / Kernel / Roofline model / CPU cache / Multi-core processor / ARC


Monitoring Performance and Power for Application Characterization with the Cache-aware Roofline Model Diogo Ant˜ao, Lu´ıs Tani¸ca, Aleksandar Ilic, Frederico Pratas, Pedro Tom´as, and Leonel Sousa INESC-ID / Institu
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Document Date: 2015-03-03 11:08:46


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File Size: 867,91 KB

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