| Document Date: 2007-08-07 14:40:04
Open Document File Size: 292,44 KBShare Result on Facebook
City Washington / DC / New York / San Jose / / Company ACM Press / Semiconductor Manufacturing / Cadence Design Systems / / Continent Europe / / Country United States / / Currency USD / / / Facility Conclusions Building / / IndustryTerm metal / hypothetical algorithm / metal layer / constructive tools / clock tree tool / satisfactory solution / considerable software / metal thickness / metal density / tool algorithms / aware constructive tools / possible solutions / clock networks / metal layers / / Organization variComputer Society / IEEE Computer Society / / Person C. Spanos / Louis K. Scheffer / Y. Cao / P. Friedberg / J. Rabaey / J. Cain / R. Wang / / Position author / extractor / physical designer / designer / Walker / and S. Narayan / digital designer / standard cell designer / SRAM designer / analog designer / Cao / / ProgrammingLanguage L / DC / C++ / / ProvinceOrState New York / California / / Technology RAM / ASCII / 4.5 Chip / dielectric / simulation / SRAM / tool algorithms / Integrated Circuits / same chip / hypothetical algorithm / CMP / / URL http /
SocialTag |
Why are Timing Estimates so Uncertain? What could we do about this? Louis K. Scheffer∗ For a specific digital gate in a specific modern technology, SPICE will give you a very specific timing number. But no one believes