Back to Results
First PageMeta Content
Graphics file formats / Archive formats / Cross-platform software / Network performance / Bzip2 / Lossless data compression / Maskless lithography / Throughput / Measuring network throughput / Data compression / Computing / Software


J. Micro/Nanolith. MEMS MOEMS 9共1兲, 013055 共Jan–Mar 2010兲 Full-chip characterization of compression algorithms for direct-write maskless lithography systems Vito Dai
Add to Reading List

Document Date: 2010-04-28 15:59:54

Open Document

File Size: 1,12 MB

Share Result on Facebook

Company

Synopsys / Vertex / /

Currency

USD / /

/

Facility

Vito Dai Avideh Zakhor George Cramer University of California Berkeley / SPIE Digital Library / /

IndustryTerm

production industry microprocessing chip / lithography systems / wireless communication applications / Manufacturing specifications / layers connecting device / search-based segmentation / asymmetric algorithm / manufacturing throughput requirement / segmentation algorithm / direct-write maskless lithography systems / communications throughput / manufacturing / compression algorithms / lossless compression algorithms / maskless lithography systems / compression algorithm / maximum board-to-chip communications throughput rcomm / required communications throughput / low-density parity code chip / lossless layout compression algorithm / decompression hardware / Optical projection systems / optical lithography systems / writer chip / volume general purpose chips / microprocessor chip / /

OperatingSystem

Windows XP / /

Organization

University of California / Tb/s Processor Board / Vito Dai Avideh Zakhor George Cramer University / ASIC / US Federal Reserve / Society of Photo-Optical Instrumentation Engineers / Adjusting Board / /

Person

Decoder-Writer Chip / Pixel / Vito Dai Avideh Zakhor George / /

/

Position

SRAM Writer / designer / writer / /

Product

Block C4 / /

ProgrammingLanguage

C / /

ProvinceOrState

Manitoba / /

Technology

chip design / three compression algorithms / low-density parity code chip / 1 The C4 algorithm / SRAM / Block C4 segmentation algorithm / lossless compression algorithms / lossless layout compression algorithm / MEMS / LDPC chip / 45-nm technology / compression algorithm / two 65-nm chips / microprocessor chip / 65-nm technology / 15 The BZIP2 algorithm / 1.2 Tb/s Processor / purpose chips / flash / three algorithms / writer chip / 64 GBit DRAM Decoder Writers Decoder-Writer Chip / JPEG / compression algorithms / production industry microprocessing chip / lithography / Block C4 lossless layout compression algorithm / decoder ASIC chip / ASIC / lithography system / ZIP algorithm / integrated circuit / /

URL

http /

SocialTag