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Iddq testing
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#	Item
1	Experimental Results for IDDQ and VLV Testing Jonathan T.-Y. Chang* , Chao-Wen Tseng* , Yi-Chin Chu* , Sanjay Wattal* , Mike Purtell* , and Edward J. McCluskey * Center for Reliable Computing Add to Reading List Source URL: crc.stanford.edu Language: English - Date: 2015-09-30 01:46:56
2	RGQS PRODUCT BRIEF E N G I N E E R I N G I N N O V A T I O N Add to Reading List Source URL: www.ridgetopgroup.com Language: English - Date: 2015-07-18 01:30:07 Integrated circuits Iddq testing Measuring instrument Standard Performance Evaluation Corporation Electronic test equipment Measurement Technology
3	Datasheet TetraMAX ATPG Automatic Test Pattern Generation Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:52 Integrated circuits Automatic test pattern generation Electronics manufacturing Electronic design Test compression Scan chain Iddq testing Joint Test Action Group Synopsys Electronic engineering Electronics Electronic design automation
4	OMAP4430 Architecture and Development Hot Chips Symposium August 2009 -------------------------------------------------------------- David Witt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:10:42 Electronic engineering Electronics 45 nanometer Iddq testing Digital signal processors ARM architecture OMAP
5	Production Technologies for Mass-production Logic LSI Yield Improvement Analysis By Means of Fault Diagnosis NIKAIDO Masafumi Abstract Add to Reading List Source URL: www.nec.com Language: English - Date: 2012-09-11 09:28:40 Systems science Failure Reliability engineering Fault Power engineering Iddq testing Failure analysis Systems engineering Maintenance Systems theory
6	Datasheet TetraMAX ATPG Automatic Test Pattern Generation Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:52 Integrated circuits Automatic test pattern generation Electronics manufacturing Electronic design Test compression Scan chain Iddq testing Joint Test Action Group Synopsys Electronic engineering Electronics Electronic design automation
7	Computer Science Technical Report Antirandom Testing: Beyond Random Testing ShenHui Wu Add to Reading List Source URL: www.cs.colostate.edu Language: English - Date: 1999-06-22 14:29:33 Electronics Integrated circuits Electronic design Digital electronics Iddq testing Fault coverage Pseudorandomness Pseudorandom generator Pseudorandom number generator Electronic engineering Algebra Electronic design automation
8	Computer Science Technical Report Antirandom Test Patterns Generation Tool Huifang Yin Computer Science Dept. Add to Reading List Source URL: www.cs.colostate.edu Language: English - Date: 1999-06-22 14:29:28 Electronics Integrated circuits Electronic design Digital electronics Iddq testing Fault coverage Stuck-at fault Reliability engineering Automatic test pattern generation Electronic engineering Electronic design automation Design
9	ITC Special Section Improving Transition Delay Test Using a Hybrid Method Nisar Ahmed and Mohammad Tehranipoor University of Connecticut Add to Reading List Source URL: www.engr.uconn.edu Language: English - Date: 2006-10-11 11:31:47 Electronic design automation Scan chain Automatic test pattern generation Electronic design Iddq testing Fault coverage Electronics manufacturing Design for testing Boundary scan Electronic engineering Electronics Integrated circuits
10	White Paper Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX™ and TetraMAX® April 2010 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:31:30 Integrated circuits Electronic design Automatic test pattern generation Scan chain Power gating Electronic design automation Power supply Iddq testing Application-specific integrated circuit Electronic engineering Electronics Design