Gate oxide

Results: 34



#Item
1High-Aspect Ratio Deep Sub-Micron α-Si Gate Etch Process Control H.-M. Park, T. L. Brock, D. Grimard, J. W. Grizzle and F. L. Terry, Jr University of Michigan 195th Spring Meeting of ECS

High-Aspect Ratio Deep Sub-Micron α-Si Gate Etch Process Control H.-M. Park, T. L. Brock, D. Grimard, J. W. Grizzle and F. L. Terry, Jr University of Michigan 195th Spring Meeting of ECS

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Source URL: web.eecs.umich.edu

Language: English - Date: 2016-04-25 13:15:12
2

Atomic layer etching of HfO2 film for gate oxide in MOSFET devices Nano Lee1, Nano Choi2, and Nano Kim1, 2, 3* 1 SKKU Advanced Institude of Nano Technology(SAINT), Sungkyunkwan University, Suwon, Kyunggi-do, Sou

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Source URL: sympo.nanokorea.or.kr

Language: English - Date: 2015-12-28 20:11:39
    3

    PDF Document

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    Source URL: www.princeton.edu

    Language: English - Date: 2006-08-19 17:00:54
    4Photon Factory Activity Report 2008 #26 Part BSurface and Interface 2C/2005S2-002 Control of oxidation and reduction in HfSiON/Si through N2 exposure Hiroyuki KAMADA*1, Tatsuhiko TANIMURA1, Satoshi TOYODA1-3, Hir

    Photon Factory Activity Report 2008 #26 Part BSurface and Interface 2C/2005S2-002 Control of oxidation and reduction in HfSiON/Si through N2 exposure Hiroyuki KAMADA*1, Tatsuhiko TANIMURA1, Satoshi TOYODA1-3, Hir

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    Source URL: pfwww.kek.jp

    Language: English - Date: 2010-01-05 10:36:03
    5Photon Factory Activity Report 2009 #27 Part BSurface and Interface 2C/2008S2003  Interfacial reactions for Ru metal-electrode/HfSiON gate stack structures studied

    Photon Factory Activity Report 2009 #27 Part BSurface and Interface 2C/2008S2003 Interfacial reactions for Ru metal-electrode/HfSiON gate stack structures studied

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    Source URL: pfwww.kek.jp

    Language: English - Date: 2010-12-27 22:22:07
    6Microsoft Wordrevised

    Microsoft Wordrevised

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    Source URL: rs.ieee.org

    Language: English - Date: 2011-06-08 19:42:34
    7AMDp2 - 5  High-Performance and Low-Temperature-Compatible Solid Phase Crystallized Polycrystalline Silicon Thin Film Transistors Using Thermal Oxide Buffered Aluminum Oxide as Gate Dielectric

    AMDp2 - 5 High-Performance and Low-Temperature-Compatible Solid Phase Crystallized Polycrystalline Silicon Thin Film Transistors Using Thermal Oxide Buffered Aluminum Oxide as Gate Dielectric

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    Source URL: www.pskl.ust.hk

    Language: English - Date: 2014-10-10 03:11:48
    8P-22: Top-Gate Thin Film Transistor with ZnO:N Channel Fabricated by Room Temperature RF Magnetron Sputtering

    P-22: Top-Gate Thin Film Transistor with ZnO:N Channel Fabricated by Room Temperature RF Magnetron Sputtering

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    Source URL: www.pskl.ust.hk

    Language: English - Date: 2014-10-10 03:11:50
    9[removed]A New Self-Aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process

    [removed]A New Self-Aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process

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    Source URL: www-mtl.mit.edu

    Language: English - Date: 2014-04-22 16:21:50
    10TF.1  Evaluation of Self-Heating and Hot Carrier Degradation of Poly-Si Thin-Film Transistors Using Charge Pumping Technique

    TF.1 Evaluation of Self-Heating and Hot Carrier Degradation of Poly-Si Thin-Film Transistors Using Charge Pumping Technique

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    Source URL: www.pskl.ust.hk

    Language: English - Date: 2014-10-10 02:44:39